1. Technical Field
The embodiments described herein relate to semiconductor integrated circuits, and in particular, to a receiver circuit for a semiconductor integrated circuit.
2. Related Art
The need for low-power supply voltage capability and high-speed interfaces is becoming more prevalent for conventional semiconductor integrated circuits as the operational speeds of such circuits increases.
Input receivers within such conventional semiconductor integrated circuits, such as semiconductor memories, are configured to buffer external signals and to transfer the signals to internal circuits and systems. The buffering operation often converts the level of the received signal to a level that is compatible with the internal circuits. In this regard, the setup and hold time is an important factor in determining the response characteristics of the receiver. Input receivers are often designed to implement one of a plurality of signal interface standards such as LVTTL, HSTL, and GTL as required by the particular circuit/system.
As transmission speeds increase it becomes more difficult to ensure a sufficient sensing margin. Further, attenuation, such as Inter-Symbol Interference (ISI), of received signals can make it difficult for the receiver to accurately sense the signals.
Therefore, equalization methods are used to ensure an adequate sensing margin, and to compensate for signal attenuation loses. In reference to equalization, an FFE (feed-forward equalization) method is disclosed in “A Reconfigurable Fully-Integrated 0.18-gm CMOS Feed Forward Equalizer IC for 10-Gb/sec Back Plane Links” (ISCAS 2006). Further, a DEF (Decision Feedback Equalization) technique is disclosed in “8-Gb/s Source-Synchronous I/O Link with Adaptive Receiver Equalization, Offset Cancellation, and Clock signal De-Skew” (IEEE JSSC Vo. 40). Furthermore, feed-back and feed-forward methods are disclosed in “A 6.4 Gb/s CMOS SerDes Core with Feed-Forward and Decision-Feedback Equalization.”
Unfortunately, circuit implementation of such solutions can be complicated and can occupy a large area, limiting integration. Further, in case of the FFE method, noise components of a signal may be amplified.